Generally, one use for delay circuits in integrated circuits (ICs) is to delay signal transmission to adjust for proper timing operation of circuit elements. In some delay circuits of the prior art, additional circuit elements are added, such as logic gates and inverters, to add delay from the additional propagation time of the signal through the added elements. However, some types of delay circuits utilize the Miller effect to provide a delay. For example, U.S. Pat. No. 4,890,022 entitled DELAY CIRCUIT DEVICE UTILIZING THE MILLER EFFECT to Endo, incorporated herein by reference, is directed to a delay line incorporating two transmission lines which are in close proximity to one another. Consequently, the two lines are capacitively coupled. When the same signal is applied to both lines, the Miller effect capacitive loading is either doubled if the two signals have opposite phase, or negligible if the signals have the same phase. Delay of a signal is determined by the phase of the signal on the second line.
More typically, the Miller Effect is used in delay circuits by providing a capacitive load to the transistor stages of a delay circuit. For example, U.S. Pat. No. 5,262,690 entitled VARIABLE DELAY CLOCK CIRCUIT to Cochran et al., incorporated herein by reference, is directed to a delay circuit for a clock signal in which a pair of differentially connected current switching transistors. Emitter follower drivers couple the switching transistors to a pair of differential delayed output terminals. A pair of diodes are cross-coupled across the differential output terminals which provide a load capacitance, which is magnified according to the gain of the transistor pair by the Miller effect. Changing the gain, therefore, changes the effective capacitance and hence, the delay, of the clock signal through the differential output terminals.
Similarly, as is known in the art, field effect transistors (FETs) have a load gate width which is seen as capacitive loading to functional circuits. Capacitive loading delays the signal passing through the delay circuit in a manner related to the time to charge the "capacitor" on the output of the functional circuit. For example, U.S. Pat. No. 5,440,260 entitled VARIABLE DELAY CIRCUIT to Hayashi et al., incorporated herein by reference, describes a functional circuit with a group of FETs arranged such that enabling the FET places the FET's capacitive load in parallel with other enabled FETs. By selectively enabling the FETs, a desired delay can be obtained.
Another reason for delay circuits on ICs is to compensate for variations in signal propagation caused by variations in parameters of the particular circuitry implemented on the IC. Such parameters may include process variations, such as circuit threshold, transconductance or topological variations, and environmental variations, such as power supply (voltage or current) and temperature variations. These variations require circuit designs with larger active devices. Driving stages experience larger loading with larger active devices which slows propagation of the signals through the devices. Consequently, load variations in different areas of circuitry on an IC may cause variations in signal propagation time through different parts of the IC.
Methods exist in the prior art to adjust circuit performance to compensate for variations in process parameters by using field effect transistors (FETs) following the functional circuits. In U.S. Pat. No. 3,970,875 entitled LSI CHIP COMPENSATOR FOR PROCESS PARAMETER VARIATIONS to Leehan, incorporated herein by reference, includes a compensating sense circuit formed as a field effect transistor circuit on an IC. The compensating circuit includes three FETs whose sensitivity is optimized such that changes in process parameters affect the output voltage. The sensing circuit compensates for load variations by adjusting the gate potential of FET load devices on the IC which are sensitive to process parameter changes.